A DRAM cell structure typically includes a metal-oxide-semiconductor field effect transistor (MOSFET) device and a capacitor that are built in or on a semiconductor silicon substrate. The MOSFET device and the capacitor form a series connection with each other. Using a word line and a bit line, a DRAM cell structure can be read and programmed.
There is a continuing trend of increasing the storage density of integrated circuit memories to provide increased quantities of data storage on a single chip. To address the challenges of reduced structure sizes, DRAM designs have been proposed which incorporate capacitors having vertical extensions above the surface of the substrate (“stacked” capacitors) or below the surface of the substrate (“trenched” capacitors). By adopting a more three-dimensional structure, such DRAM designs provide memory capacitors having larger capacitance while occupying less surface area of the substrate.
However, when the critical dimension of a DRAM cell structure is reduced to sub-20 nm scale, the occupied area is too small to allow formation of a capacitor with a very tall, vertical cylinder shape using current photolithography and etching processes. Therefore, there is a need for providing a method of preparing a capacitor having high capacitance in a DRAM cell structure.
This Discussion of the Background section is for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this section constitutes a prior art to the present disclosure, and no part of this section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure.